Data storage having multiple channels typically employs movable media in which data is recorded on one pass of the media, and the data is read back and detected at a subsequent time, possibly on a different pass of the media and possibly on a different drive than that which recorded the data. One example of movable media is magnetic tape which has a plurality of parallel tracks for recording. The parallel tracks are typically written simultaneously such that the signal clocking of the signals written on parallel media are correlated.
Symbol timing recovery during readback represents one of the most critical functions in data storage read channels. Sampling an analog readback signal at the right time instant is important for achieving good overall performance. Among the challenges presented are the presence of disturbances such as dropout events, instantaneous speed variations, and signal distortion of various origins, which make timing recovery difficult. As areal recording densities become higher and higher, SNR (signal to noise ratio) margins are decreased, making satisfactory timing recovery an even more challenging task.
Timing recovery typically is based on a PLL (phase locked loop) for each channel whose purpose is to accurately estimate the timing offsets before sampling the analog signal. Problems in this context, especially with degraded channel conditions as explained above, are those of temporary “loss of lock” or “cycle slip”. These terms refer to a phenomenon where the phase adjustments of the timing control loop stabilize around an undesirable phase value that is located one or several symbol interval durations apart from the desired operating point. This phenomenon often results in long bursts of bit and symbol errors which may exceed the error correction capability of the error correction codes, such as Reed-Solomon codes, leading to severe performance degradation or even permanent error situations.
The conventional approaches have been to optimize the operation of the PLL for maximum noise rejection and loop jitter minimization, to increase the loop robustness by using more reliable decisions, etc.
The incorporated '315 patent, inter alia, takes advantage of the multiple channels by providing a global clock which generates a global average frequency signal by averaging the content of the frequency registers employed by the PLLs of the individual channels. The global average frequency is employed by the PLL of each track which adds its own scaled phase error to it.